This invention relates, in general, to semiconductor memories, and more particularly, to a memory useful in a video graphic system.
Video graphic systems require a great deal of memory capacity. One of the most critical memory requirements for a video graphic system is the rate at which data must be read from the memory to refresh the cathode ray tube (CRT) display. Data rates of eight to fifty M bytes/sec are common. Next is the ability of the memory to have additional bandwidth to allow update of the memory without interfering with the video refresh of the CRT. The third priority is the ability to asynchronously change the data flow to another address sequence within a reasonable time. This third requirement is needed to handle smooth scrolling and multiple windows to the memory. With present memory architecture of a dynamic RAM, the data path depth must be increased to handle increased bandwidth. This increases the memory chip count and decreases the optimal size depending upon the number of display frames required. For higher density displays which require higher bandwidth, larger memory sizes are not the most efficient approach to take. In addition, it is also desirable to write into the memory at the same time that the memory is being used to refresh the CRT display.
One suggested memory had a shift register which received an entire row of data. However, since a picture frame will likely start on other than a boundary established by the first bit to be shifted out, such a memory is not considered totally satisfactory. Also this type of memory does not allow for the boundary to be changed while sequencing data for a horizontal line.
Therefore, there is a need for an architecture of a memory chip which can perform a CRT display refresh cycle by placing multiple bytes into a shift register which can then be shifted out independent of the standard access.
Accordingly, it is an object of the present invention to provide an improved memory chip.
Another object of the present invention is to provide a memory which has the capability to shift data out independently from the normal access to a standard memory.
Yet another object of the present invention is to provide a memory which can serially shift data out at a high rate of speed while providing access to odd boundaries of a CRT display associated with the memory.